Applies To:
  • CitectSCADA 1.00, 1.01, 1.10, 1.11, 2.00, 2.01

This information assumes to know how to use the Citect debugging kernel.

If the performance of Citect is sluggish there are many diagnostic tools that allow you to trace the cause of the problem. Slow response can be caused by two main problems:

  1. Slow PLC communications.
  2. CPU Overload.

When you change pages, if the background graphics are displayed quickly, but there is a long delay before they are animated, then the response time from the PLC is the cause. When Citect changes pages, it first requests all data from the I/O Server, then starts to draw the background image. While Citect is drawing the background image the I/O Server will be reading the required data from the PLCs. When Citect has finished drawing the background image it will wait for all the data to come back from the I/O Server before animating the page - the page will not be animated until the very last piece of data has been returned. This will mean that the update of the page will be dependent on the slowest PLC response time. If you have 1 slow PLC, it will effect the animation time.

If Citect is generally sluggish, for example when you hit a key to change pages it takes a little while even before the background animation starts to be displayed, then the CPU may be overloaded. In the debug Kernel check the CPU usage. If the CPU usage is higher than 60% most of the time, the computer is overloaded. You may want to trend the CPU value by using the CitectInfo function to give you a better view of what is happening. 

See Q1060 and Q1061 for more details.