Applies To:
  • CitectSCADA 3.x 4.x 5.x
Summary:
Each analog value in a PLC normally occupies a word location (16 bits wide). The first word will be V1 and the next will be V2, V3, V4 and so on. Some PLC allows its values to be accessed as long or real (32 bit wide) which will use two words in the PLC. The first long will be V1 and the next will be V3, V5, V7 and so on. Using the even addresses (V2, V4) as long variable will be invalid in this case. The CITECT compiler fails to issue an error when even addresses are used to access long variables.  

Solution:
The compiler in version 3.0 will check that the address of variables are aligned properly when accessing
  • Word in the PLC as long or real
  • Byte in PLC as word, long or real
  • The first long or real accessed will set the origin if no '%Qn' is specified.
  • The compiler will give the error "Address on bad boundary" when subsequent variables are not aligned the same as the first variable.

If the user wants to access even addresses as longs in one-origin addressing for a particular data type he would have to append a '%Qn' specification for that variable type in the variable template file. For example if he wants to use V2 in TIWAY as long, he would have to change the 'V%U' in the TIWAY.DBF file to 'V%U%Q1'. '%Q0' is the default for all data types. If he wants to turn the address boundary checking off for all V's, he would change the 'V%U' in the TIWAY.DBF file to 'V%U%Q2', or to any other number other than 0, 1 or 255.

This compile time check can be turned off globally by setting

[general]CheckAddressBoundary = 0

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