| Applies To: |
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| Summary: |
| DIGITAL aliases cause sub-optimal performance with ABCLX |
| Solution: | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| The Allen Bradley protocol
(CLX) implements bit aliasing in such a way that each aliased bit
from a controller tag consumes an entire byte. For Example, to
request all 8 aliased bits from a single byte will generate 8 bytes
of data that is polled across the network even though the same
information could be requested in a single byte. This would be done
by using the ABCLX bit syntax
For Example: Below are eight digital aliases created in the PLC for a tag with address "Tag1". Each of these digital tag aliases will consume 1 byte each as described above.
To use these aliases on citect end, you will need to create tags with addresses as shown below
Instead of the above approach, Bit addressing can be used, which would not require you to create a digital alias on the PLC but the same digital bits can be addressed in citect using the follwoing addressing syntax. So for a tag addrees "Tag1" in PLC end, digital tags mapped to individual bits would be defined as below
This would acquire all of the information in a single byte as ABCLX recognises multiple requests for data and makes requests in the most efficient way possible - in this case it requests the single byte and Citect extracts all eight bits from this single byte. This means that you can gain 8 times the efficiency purely by using the ABCLX bit access syntax over the aliasing of the bits in the PLC. NOTE: The above mentioned approach suggests using ABCLX bit access for optimal system performance but final evaluation of PLC logic to capture any changes to the control logic should be carried out by end users themselves. |
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