Product : ISaGRAF 3.3
Date : 18-August-1998
File : align.Target alignment considerations .htm
Subject : Target alignment considerations
Keywords: Alignment - ISA_ALIGN - tasy0def.h - SYSTEM
The alignment is defined by rules applied to the address location
where data is to be allocated according to its type. For example
with an alignment at 4, it generaly means that:
- 16 bits variable is to be allocated at an address multiple of 2
- 32 bits variable is to be allocated at an address multiple of 4
This is also true within structures. Therefore it may leads to
gaps between different fields of a structure.
These alignment constraints are closely linked to the hardware, the
CPU and, in the end, the compiler. For instance some CPUs cannot
access a long (32bits) variable at an address non multiple of 4.
As a consequence you get a bus error or something similar.
In some other cases (Intel x86, pentium CPUs or some Motorola
Power Pc) it is just for execution speed concerns.
On previous target versions, the alignment value was fixed to 2 (1
is obviously ok)
The result of an alignment mismatch can then either be a system
error or some data mismatches between target structures and
workbench generated application code. Any way it does not work.
From target 3.3 version, some modifications have been made to try
to make it work with an alignment different from 2 (generaly 4).
In that way, the IDK customer needs to define ISA_ALIGN macro in the
definition file (tasy0def.h) with its system alignment. When not
defined in this file, the default value is 2 (this keeps
Any way, some parts are still not taken into account by this
alignment. They are:
- IOs OEM data. This can be worked arround in defining some
constraints: The IO integrator must declare homogeneous
oem data such as there is no alignment mismatches.
- Call to the ISaGRAF SYSTEM function for saving ALL. This can be
worked around by calling the function several times for each
- All points not discovered yet...Please tell us
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