Additional information

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Description

CPU 212

CPU 214

CPU 215

CPU 216

Size of user program

512 words

2 K words

4 K words

4 K words

Size of user data

512 words

2 K words

2.5 K words

2.5 K words

Process image of inputs

E0.0 to E7.7

E0.0 to E7.7

E0.0 to E7.7

E0.0 to E7.7

Process image of outputs

A0.0 to A7.7

A0.0 to A7.7

A0.0 to A7.7

A0.0 to A7.7

Analog inputs (read only)

AEW0 to AEW30

AEW0 to AEW30

AEW0 to AEW30

AEW0 to AEW30

Analog outputs (write only)

AAW0 to AAW30

AAW0 to AAW30

AAW0 to AAW30

AAW0 to AAW30

Variable memory (V)
Resident area
(max.)

V0.0 to V1023.7

V0.0 to V199.7

V0.0 to V4095.7

V0.0 to V1023.7

V0.0 to V5119.7

V0.0 to V5119.7

V0.0 to V5119.7

V0.0 to V5119.7

Marker (M)

Resident area

(max.)

M0.0 to M15.7

MB0 to MB13

M0.0 to M31.7

MB0 to MB13

M0.0 to M31.7

MB0 to MB13

M0.0 to M31.7

MB0 to MB13

Special marker (SM)

Write-protected

SM0.0 to SM45.7

SM0.0 to SM29.7

SM0.0 to SM85.7

SM0.0 to SM29.7

SM0.0 to SM194.7

SM0.0 to SM29.7

SM0.0 to SM194.7

SM0.0 to SM29.7

times

64 (T0 to T63)

128 (T0 to T127)

256 (T0 to T255)

256 (T0 to T255)

Retentive
on-delay 1 ms

T0

T0, T64

T0, T64

T0, T64

Retentive
on-delay 10 ms

T1 to T4

T1 to T4, T65 to T68

T1 to T4, T65 to T68

T1 to T4, T65 to T68

Retentive
on-delay 100 ms

T5 to T31

T5 to T31, T69 to

T95

T5 to T31, T69 to

T95

T5 to T31, T69 to

T95

on-delay 1 ms

T32

T32, T96

T32, T96

T32, T96

on-delay 10 ms

T33 to T36

T33 to T36,

T97 to T100

T33 to T36,

T97 to T100

T33 to T36,

T97 to T100

on-delay 100 ms

T37 to T63

T37 to T63,

T101 to T127

T37 to T63,

T101 to T255

T37 to T63,T101 to T255

Counters

Z0 to Z63

Z0 to Z127

Z0 to Z255

Z0 to Z255

Fast counters

HC0

HC0 to HC2

HC0 to HC2

HC0 to HC2

Sequence control relay

S0.0 to S7.7

S0.0 to S15.7

S0.0 to S31.7

S0.0 to S31.7

Accumulators

AC0 to AC3

AC0 to AC3

AC0 to AC3

AC0 to AC3

Jumps/jump labels

0 to 63

0 to 255

0 to 255

0 to 255

Calls/Sub programs

0 to 15

0 to 63

0 to 63

0 to 63

Interrupt programs

0 to 31

0 to 127

0 to 127

0 to 127

Interrupt events

0, 1, 8 to 10, 12

0 to 20

0 to 23

0 to 26

PID Regulator

Not supported

Not supported

0 to 7

0 to 7

Interfaces

0

0

0

0 and 1

The table is just an example. Please look up the exact areas in the documentation of the PLC.